`timescale 1ns / 1ps

module v_speed_debouncer(
    input clk,                      // 时钟信号
    input rst_n,                    // 复位信号，低电平有效
    input invs,                     // 输入信号，待去抖动的信号
    output reg outvs                // 输出信号，去抖动后的信号
);
reg[2:0] counter;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		counter<=3'd0;
		outvs<=1'b0;
	end
else 
	begin
		if(invs)
			begin
				counter<=3'b0;
				outvs<=1'b0;
			end
		else
		begin
		if(counter<3'd7)
			begin
				counter<=counter+1'b1;
				outvs<=1'b0;
			end
		else 
			begin
				counter<=counter;
				outvs<=1'b1;
			end
		end
	end


end



endmodule
